cache disable

출처 : http://www.df.lth.se/~john_e/gems/gem000b.html

출처 : http://stackoverflow.com/questions/21265785/enable-disable-cache-on-intel-64bit-machine-cd-bit-always-set

My question is:

Is the CD bit(30bit) of CR0 register always set 1 when cache is disabled?

If not, there must be something wrong with my code, could you please help me point out the error I made?

ANSWER:

The above code only set the CD bit of the CR0 register on the core where the code is running. We need to use the smp_call_function() to call the code on all cores!

; Disable the Cache(s)
;
; input:
;   none
;
; output:
;   none
;
; destroys:
;   noting - (except switching flags)
;

CR0_CD  EQU     040000000h      ; Cache Disable bit of CR0
CR0_NW  EQU     020000000h      ; Not Write-through bit of CR0

        pushf                   ; save the flags
        push    eax             ; save eax
        cli                     ; disable interrupts while we do this
        mov     eax,cr0         ; read CR0
        or      eax,CR0_CD      ; set CD but not NW bit of CR0
        mov     cr0,eax         ; cache is now disabled
        wbinvd                  ; flush and invalidate cache

        ; the cache is effectively disabled at this point, but memory
        ; consistency will be maintained. To completely disable cache,
        ; the following two lines may used as well:

        or      eax,CR0_NW      ; now set the NW bit
        mov     cr0,eax         ; turn off the cache entirely
        pop     eax             ; restore eax
        popf                    ; restore the flags
        ret                     ; return to caller